Aldec Releases Xilinx® Foundation Series™ Legacy Design Import Utility

Henderson Nevada, December 3rd, 2002 -- Aldec, Inc., a pioneer in mixed language simulation and advanced design tools for FPGA and ASIC devices, today announced that designers who use Xilinx Foundation legacy schematics in their latest designs can port them directly into Active-HDL’s high performance, mixed language simulator to be implemented in any Xilinx device. Aldec provides its customers with a utility to import existing Foundation schematics directly into Active-HDL to support Xilinx’s next generation of high-density Spartan™ and Virtex-II™ devices.

Seamless Migration
Aldec initially authored and developed all of the design editors and project managers for the Xilinx Foundation Series software, and it now uses that same technology to provide seamless porting of Foundation schematics into its Active-HDL environment. The ported schematics are translated into HDL block diagrams and are graphically represented as their native schematics files that previously existed in Foundation. Such effortless conversion of modules permits native schematic files to be re-used and applied to new designs targeting Xilinx FPGA devices.

Active-HDL’s support of Foundation schematic designs speeds the design cycle and minimizes the number of errors, as designers can use the pre-existing schematic modules instead of having to re-create the designs in HDL code. By supporting both schematics and HDL modules in a single environment, Active-HDL allows designers to re-use legacy designs in support of new Xilinx devices.

Supporting EDIF
Active-HDL’s support of EDIF modules allows Foundation users to simulate mixed schematic and HDL designs at the gate level. Active-HDL also supports Xilinx CORE Generator™, ABEL and LogiBLOX™ modules, and is the most universal verification platform to test the functionality of all modules prior to being implemented in the Xilinx architecture. Active-HDL supports mixed EDIF, VHDL and Verilog simulation; designers can use an HDL testbench or the existing simulation macros from Foundation to verify the accuracy of their designs.

Synthesis Tools Supported
Active-HDL allows designers to use any combination of synthesis and Xilinx implementation software, making it the most flexible, cost-effective tool on the market. Active-HDL supports all industry leading tools, including Synplify™, Synplify Pro™, Synopsys’ FPGA Express™, Xilinx’s proprietary XST synthesis and all other FPGA synthesis technologies. A direct interface to previous versions of Xilinx’s Foundation, 4.1i and 4.2i, in addition to ISE 5.1i, are supported in the flow. Companies and designers using a specific version of Xilinx implementation tools can select the location of that software in the Active-HDL Flow Manager, which will process the design accordingly.

Availability
Aldec’s Active-HDL tool seamlessly imports Foundation legacy designs into a BDE format; Active-HDL may be purchased as either a vendor independent version, or an application specific to Xilinx devices. The Xilinx Edition (XE) may be purchased as a perpetual or time-based license. Active-HDL 5.2 includes Multi-Design Workspace, HDL Editor, State Machine Editor, and Block Diagram & Schematic Editors, Automatic Testbench Generation, Waveform Viewer/Editor, and a choice of VHDL, Verilog or mixed VHDL/Verilog/EDIF simulation. All sales include one year of product maintenance. To receive your FREE evaluation copy, contact Aldec at www.aldec.com.


About Aldec
Aldec, Inc., an 18-year EDA tool provider, is committed to delivering high-performance, HDL-based design verification software for UNIX, Linux and Windows platforms. Aldec is dedicated and responsive to serving its customers’ needs with its offices located around the globe. Continuous innovation, superior product quality and total commitment to customer service comprise the foundation of Aldec’s strategic objectives. Additional information about Aldec is available at http://www.aldec.com.